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Driving Methods

SPI
A serial peripheral interface (SPI) is an interface that enables the serial (one bit at a time) exchange of data between two devices, one called a master and the other called a slave . An SPI operates in full duplex mode. This means that data can be transferred in both directions at the same time. The Serial Peripheral Interface or SPI‐bus is a simple 4‐wire serial communications.
An SPI protocol specifies 4 signal wires.
1) Master Out Slave In (MOSI) ‐MOSI signal is generated by Master, recipient is the Slave.
  1. 2) Master In Slave Out (MISO) ‐Slaves generate MISO signals and recipient is the Master.
    3) Serial Clock (SCLK or SCK) ‐SCLK signal is generated by the Master to synchronize data transfers between the master and the slave.
    4)Slave Select (SS) from master to Chip Select (CS) of slave ‐SS signal is generated by Master to select individual slave/peripheral devices. The SS/CS is an active low signal.
    I2C
  2.  
The basic design of I²C has a 7‐bit address space with 16 reserved addresses, which makes the maximum number of nodes that can communicate on the same bus as 112. That means each I²C device is recognized by a unique 7‐bit address. It is important to note that the maximum number of nodes is obviously limited by the address space, and also by the total bus capacitance of 400 pf. The two bi‐directional lines, which carry information between the devices connected to the bus, are known as Serial Data line (SDA) and Serial Clock line (SCL). As the name indicates the SDA line contains the data and the SCL with the clock signal for synchronization. The typical voltages used are +5 V or +3.3V.

Serial

A serial communications interface (SCI) is a device that enables the serial (one bit at a time) exchange of data. In this respect, it is similar to a serial peripheral interface (SPI ). But in addition, the SCI enables serial communications with other microprocessors. The SCI contains a parallel‐to‐serial converter that serves as a data transmitter, and a serial‐to‐parallel converter that serves as a data receiver. The two devices are clocked separately, and use independent enable and interrupt signals. The SCI operates in a non‐return‐to‐zero (NRZ ) format, and can function in half‐duplex mode (using only the receiver or only the transmitter) or in full duplex (using the receiver and the transmitter simultaneously). The data speed is programmable.

Parallel

A parallel interface means that the microcontroller has to manipulate several interface pins at once to control the display. The interface consists of the following pins:
A register select (RS) pin that controls where in the LCD/OLED's memory you're writing data to. You can select either the data register, which holds what goes on the screen, or an instruction register, which is where the LCD/OLED's controller looks for instructions on what to do next.
A Read/Write (R/W) pin that selects reading mode or writing mode
An Enable pin that enables writing to the registers
8 data pins (D0 ‐D7). The states of these pins (high or low) are the bits that you're writing to a register when you write, or the values you're reading when you read.
There's also a display contrast pin (Vo), power supply pins (+5V and GND) and LED Backlight (Backlight+ and Backlight‐) pins that you can use to power the LCD/OLED, control the display contrast, and turn on and off the LED backlight, respectively.
The Hitachi‐compatible LCD/OLEDs can be controlled in two modes: 4‐bit or 8‐bit. The 4‐bit mode requires seven I/O pins, while the 8‐bit mode requires 11 pins. For displaying text on the screen, you can do most everything in 4‐bit mode.

Parallel Interface Types
  • Bit Data ‐Used on some monochrome QVGA modules. An option on character controllers
  • 8 Bit Data ‐Most Common ‐used on graphic and character controllers
  • 16 Bit Data ‐Not Common ‐used on some graphic controllers
  • 6800 type ‐Parallel Data, with Read/Write Line, Enable Line
  • 8080 type ‐Parallel Data with Write Line, Read Line
 
Other driving methods include LVDS, DSI, and MIPI – contact our Engineering team for assistance

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